TSMC

Battery Life

I wish my first generation iPhone battery stayed charged just a bit longer to last through my frequent flights between California and Asia. With so many things to do on the phone these days --  videos, music, games, navigation, and Internet (but not on the plane, of course) --- not counting phone calls themselves, it would be nice if the iPhone 3G that just came out on market would last the whole day on active, and over a week on standby.

Being responsible for design methodology integration and deployment, including design tools and flows at TSMC, I visited a number of chip design companies and spoke to their design teams about chip power requirements. It’s not too surprising that low power consumption is on top of every team’s list.  Most of the time it’s a higher priority than chip speed or die area, the other two major chip specs.

Chip designers need to take a comprehensive approach, I believe, to fully address the power issue, starting from the architecture design phase, then RTL/gate/circuit level, and process level.

On the process side, TSMC has been providing low power silicon processes for sometimes, beginning at the 90nm process node where power consumption starts to become a major issue. Our offerings include low operating voltage, multiple threshold devices, and other options to reduce chip power.

At RTL, gate and circuit levels, the latest TSMC Reference Flow provides designers a number of low power design techniques, such as voltage/power islands, power shutdown, voltage scaling, back biasing, clock gating, etc. to reduce chip dynamic and standby power consumption. Some power reduction techniques are simple. Others are much more complex and require in-depth knowledge of the design to ensure that all of these power techniques work in tandem with all the intended chip functions.

TSMC recently introduced Power Trim Service to help reduce leakage power, one increasingly problematic component of total chip power consumption. TSMC Power Trim Service using an unique power reduction software technology co-optimizing with TSMC special tuned manufacturing process to further reduce chip leakage power above and beyond the current power reduction techniques already employed on chip.

Given these innovations in low power design and availability of advanced low power silicon process technologies, my wish for the next generation smartphone is that its ability to last for days of active usage would be more than a dream. Who knows, maybe that capability will be available within a few years.
 

-Tom Quan

What kind of car do you drive?

As a TSMC program manager, I recently penned a chapter called “CMOS Technology as an Emerging Technologies System Driver” for a book, which will come out shortly. The gist of this introductory chapter is that CMOS and its derivatives (CMOS +: embedded Flash, embedded DRAM, high voltage, CMOS image sensors, mixed-signal/RF, Silicon Germanium) provide an incredible backbone on which to build innovations. I concluded the chapter with the following analogy “In sum, one can imagine CMOS is a bit like the interstate highway system while CMOS+ is the local highway network. They both allow you to explore new territory in a very fast and efficient way. Of course, you will still need to take the dirt tracks on the side and even walk a bit to create something truly new.”

The idea is that both CMOS and the highway system are infrastructures that require tremendous initial investments but that are affordable and available to use for everyone with a purpose. And then I got to thinking: Just for the fun of it, what if I pushed this metaphor just a little further.

Imagine you are driving along this wonderful highway system, what kind of car would you drive? Do you take a fuel-efficient hybrid to travel cheaply? You may want a 4x4 to explore those dirt tracks, and sometimes, you might need a recreational vehicle, to spend the nights prospecting near those dirt paths. A Ferrari could come in handy when you need speed on those curvy mountain roads. At the other extreme, you may also need to use an 18- wheeler to move a lot of stuff. Many times we want a combination of all of the above but we are forced to make a compromise and pick one vehicle for the entire journey. But does it need to be case? Wouldn’t it be nice to be able to switch on demand?

Back in the world of CMOS, we do provide the equivalent to this ideal vehicle: a great variety of services and options enabling rapid and efficient product innovations. We start with a cost saving design stage and good roadmaps to guide you to your destination. We then leverage a tremendous breadth of technologies and engineering resources for special cases. Once ready, you can get bursts of speed with super hot lots, and world class cycle time. Product proven, a huge capacity is there just ready to move volume. And our reliability gives you peace of mind as you drive. Best of all, no compromise; you get best in class services each step of the way, all from one foundry choice.

Did I take the metaphor too far? Maybe, but remember, this was just for the fun of it! Let me know what you think and…what kind of car do you want to drive?

-Paul Rousseau

Do you node-compromise to compete?

I recently ran into a friend who started a chip design company about a year ago. He just completed his first round of funding that resulted in a good amount of money being invested in the company. He complained to me that half of this funding round will probably be spent on building the required “design infrastructure” to support his company’s first chip design. His comment got me thinking about chip design costs at the most advanced process node. In order to stay competitive, his company must reduce design costs in order to deliver the first chip before first round money runs out.

Semiconductor design cost continues to increase at every successive semiconductor process generation. Recent market research reports suggest that the cost of designing a system-on-chip (SoC) in 40nm process technology will exceed $50 million. Given this cost, there are probably only a few chip companies that can afford to do designs at this process node. And my friend’s company is definitely not one of them. So what happens to all the start-ups and small companies with promising “killer” applications? Must they be content to be less competitive by designing at less advance processes in order to hold the line on design costs?

A quick look at the design cost components reveals that a good portion are “design infrastructure” cost, including cost to develop, evaluate, maintain, and support design tools, flows, and methodologies to enable design teams to innovate. For large companies, this cost is significant because they need to support multiple flows and methodologies to support multiple design teams targeting a diverse set of end applications. For start-ups and small companies whose life expectancy depends on one “killer” chip, the design infrastructure cost is prohibitively large.

So how can my friend’s company, as well as other smaller companies innovate, get their chips out the door, and win customers on a much smaller design infrastructure budget?

My suggestion: They should collaborate with a foundry like TSMC and leverage the design infrastructure built for them by the foundry.

At TSMC, for example, we’ve already invested significant time and resources into building a comprehensive design infrastructure needed for next generation chip designs targeting our advanced process technologies. We qualify and validate EDA tools, so our customers don’t have to. We develop reference design flows and methodologies for most common design applications, so our customers can reduce and even eliminate lengthy and costly flow development and evaluation, and start their designs quickly. We enable design tools to be “plug and play” with reference design flows by establishing standardized and interoperable interfaces between tools and flows, and validating them.

With the TSMC supported “design infrastructure,” I think my friend can focus his company time and money to bring his innovation to market quicker and less cost. That would be music to the ears of his investors.

-Tom Quan

Grade A performance

After a short trip to the California last week I had a couple of hours to kill and was unable to resist popping into Fry’s Electronics to check out the special deals. Whilst browsing between the pallets I found the perfect motherboard to upgrade my Media PC at home so put it in my basket and went to select an appropriate CPU.

Having decided that I wanted an Intel Core 2 Duo I was then confronted by the problem of which one of the five variants I should choose? The Sales assistant kindly suggested I take the most expensive variant on the basis that it was “very popular” despite it costing more than twice the price of the cheapest variant.

Whilst there was a difference in the cache size for the cheapest variant, the others seemed fundamentally to be the same except for the maximum quoted clock speed but obviously this difference in performance (or perhaps just the perceived difference) was enough to justify the price for some consumers. In fact checking Fry’s web-site, I see today that the high-end variant is currently out of stock whilst the low-end is still available so it seems that this may really be “very popular” or perhaps it is in short supply.

The manufacturing of such chips at Intel is a highly complex process and despite very tight control of all the parameters each individual chip that is produced will still show some small differences from the others chips, some may be faster whilst other slower, some may require more power and other less. In many cases it is these manufacturing differences that are used to differentiate products and the small number of chips which happen to follow the ideal manufacturing flow and as a result run 10% faster than the others are the ones that are sold off at a premium – this is a process called binning (or speed grading) and has been used for many years.

As part of its manufacturing excellence TSMC has always worked with customers to ensure that they got the highest number of parts from the top bins, however this has always been done as part of a continual improvement effort after the design has been completed and the first products produced. The Intel Core2 Duo example is a good analogy for a new service called “Product Grade” technology whereby TSMC plans to provide roadmaps on how the speed, power and other parameters of a technology could be improved over its lifetime and with which variances. By selecting this service, customers can make much earlier design decisions that can really take advantage of these improvements in a systematic way so that they can then really target all their products into the optimum bins and in doing so maximise their selling price.

At least this would simplify my choice next time I am at Fry’s (in the end I purchased the mid-range on the basis of it giving the best bang for my Euro).

-Douglas Pattullo