I wish my first generation iPhone battery stayed charged just a bit longer to last through my frequent flights between California and Asia. With so many things to do on the phone these days -- videos, music, games, navigation, and Internet (but not on the plane, of course) --- not counting phone calls themselves, it would be nice if the iPhone 3G that just came out on market would last the whole day on active, and over a week on standby.
Being responsible for design methodology integration and deployment, including design tools and flows at TSMC, I visited a number of chip design companies and spoke to their design teams about chip power requirements. It’s not too surprising that low power consumption is on top of every team’s list. Most of the time it’s a higher priority than chip speed or die area, the other two major chip specs.
Chip designers need to take a comprehensive approach, I believe, to fully address the power issue, starting from the architecture design phase, then RTL/gate/circuit level, and process level.
On the process side, TSMC has been providing low power silicon processes for sometimes, beginning at the 90nm process node where power consumption starts to become a major issue. Our offerings include low operating voltage, multiple threshold devices, and other options to reduce chip power.
At RTL, gate and circuit levels, the latest TSMC Reference Flow provides designers a number of low power design techniques, such as voltage/power islands, power shutdown, voltage scaling, back biasing, clock gating, etc. to reduce chip dynamic and standby power consumption. Some power reduction techniques are simple. Others are much more complex and require in-depth knowledge of the design to ensure that all of these power techniques work in tandem with all the intended chip functions.
TSMC recently introduced Power Trim Service to help reduce leakage power, one increasingly problematic component of total chip power consumption. TSMC Power Trim Service using an unique power reduction software technology co-optimizing with TSMC special tuned manufacturing process to further reduce chip leakage power above and beyond the current power reduction techniques already employed on chip.
Given these innovations in low power design and availability of advanced low power silicon process technologies, my wish for the next generation smartphone is that its ability to last for days of active usage would be more than a dream. Who knows, maybe that capability will be available within a few years.
Tom;
Thanks for the blog and taking the time to post.
I am fascinated by where portable and handheld device desgin is going with newer battery technologies such as Lithium manganese and smart design for the UI, I ca nsee a day where we will be able to replace the desktop / notbook PC format with an iPhone like device.
A critical part of this is going to be power management so I an interested to keep up to date on these issues.
Regards Pete.
Posted by: Pete | January 05, 2009 at 03:06 PM